The technical field of this invention is digital data processors especially those including direct memory access units which can self-modify their data transfer parameters.
In design of microprocessors and particularly digital signal processors (DSP) the need for autonomous data movement via a direct memory access (DMA) controller has become increasingly common. The ability to perform complex data transfers within a memory hierarchy without central processing unit interventions offers substantial system performance benefits by offloading the data movements tasks from the central processing unit. This is particularly helpful for central processing unit which are not natively optimized to control data movement. For example, a digital signal processor might include four to eight parallel functional units, each capable of executing an instruction in a single machine cycle. Of these eight units however, typically only one or two will be capable of controlling memory transfers. Hence, using the central processing unit to perform memory moves is inefficient and degrades system performance. As a consequence, a direct memory access controller becomes a powerful system peripheral.
In order for a direct memory access to be utilized most efficiently, it will generally include one or more channels. A DMA channel generically refers to the context of a memory transaction. Such a context might include the source and destination address of the transaction, a data transfer count, plus any special transfer options that the controller supports. The context of each channel is typically managed by the direct memory access unit and is stored in some storage element. This storage element is typically a RAM or register set. The central processing unit of the system generally has access to these context elements, but will typically access them only for transfer initialization and status monitoring.
FIG. 1 illustrates a channel controller of typical known direct memory access unit. Implementations of direct memory access units may vary widely, but the elementary conventional direct memory access controller channel illustrated in FIG. 1 is suitable for the purpose of explanation. The major task of the direct memory access controller is to generate the source (SRC) address, the destination (DST) address and the transfer count. Register 100 holds the source address which is updated through multiplexer 103 in the run condition and recirculated via path 105 in the case of a stall. Updating the source address consists of addition with a 1 word address increment to the next address location via adder 102. Reload parameters and central processing unit data updates are inserted through multiplexer 104 when auto load or central processing unit write operations are activated.
Similarly register 110 holds the destination address which is updated through multiplexer 113 in the run condition and recirculated via path 115 in the case of a stall. Updating the destination address consists of addition with a 1 word address increment to the next address location via adder 112. Reload parameters and central processing unit data updates are inserted through multiplexer 114 when auto load or central processing unit write operations are activated.
Register 120 holds the data transfer count which is updated through multiplexer 123 in the run condition and recirculated via path 125 in the case of a stall. Updating the data transfer count consists of subtraction with a 1 word address increment to the next transfer count via adder 122. Reload parameters and central processing unit data updates are inserted through multiplexer 124 when auto load or central processing unit write operations are activated. In addition the run/stall signal is generated from a logical combination of channel exhaust condition (zero data transfer count) and the channel request signal generated external to this block.
A common use of a direct memory access engine is for the maintenance of double buffers. In a double buffering scheme, the central processing unit of the system will own one of the buffers, which it uses to process data. The direct memory access will own the other buffer and will write data to or read data from the buffer. The direct memory access unit is typically driven from a real-time system event. For example, in a capture buffer scheme action is as follows.
In direct memory access writes to buffers, the triggering direct memory access event might be a xe2x80x9creadyxe2x80x9d signal from an analog-to-digital (A/D) converter, which tells the direct memory access unit that a sample is ready and should be read from the analog-to-digital converter and placed into memory. Each event from the analog-to-digital converter to the direct memory access unit tells the direct memory access unit to move one data word corresponding to an analog sample from the source in the analog-to-digital converter to a destination in one of the double buffers. The direct memory access unit performs this transaction and typically also updates the destination address so that the next sample will be written to the next sequential destination address. Note that decrementing destination addresses and indexed addressing modes are also common. The direct memory access unit will also decrement the data transfer count, so that the end of the data transfer can be detected when the data transfer count reaches zero. The event from the analog-to-digital converter to the direct memory access unit will occur many times during the course of filling one of the buffers in a double buffering scheme.
The typical double buffering technique is illustrated in FIG. 2. Analog-to-digital converter 200 supplies a data ready signal to direct memory access controller 201 in response to the source address 203. Direct memory access controller 201 in turn generates the destination addresses for the two banks of capture buffers 204 and 205. The interleaving of the direct memory access read/write activity with direct memory access idle time 206 and analog-to-digital converter data ready signals 207 is shown in the timing diagram.
At some point in time, the buffers must be switched, such so that the central processing unit can process the newly sampled analog-to-digital data. When the buffers are switched, the central processing unit is given access to the buffer that the direct memory access unit formerly owned and the direct memory access unit assumes ownership of the buffer that the central processing unit formerly owned. In order not to lose any data sample, this switch will occur as a result of an interrupt 210 from direct memory access unit 201 to the central processing unit generated upon occurrence of event 211 when the channel data transfer count has reached zero. This indicatives a full buffer. The interrupt informs the central processing unit that the direct memory access unit has filled a new buffer and that the direct memory access unit intends to assume control of the other buffer so that it can continue capturing the real-time data stream from analog-to-digital converter 200.
At this point, it is generally necessary that the direct memory access channel parameters be reloaded, since the transfer count is now zero and the destination address has updated to a value no longer in the range of one of the double buffers. The reload of parameters into the direct memory access channel storage can occur via several methods. Historically, this has occurred as a result of the central processing unit performing a series of accesses to the direct memory access unit storage elements during the interrupt service routine in response to the aforementioned interrupt. This operation is also illustrated at times 212 and 213 in FIG. 2.
While effective in some situations, as the number and complexity of direct memory accesses in a system increase this service requires a greater amount of central processing unit intervention and thus degrades system performance. To combat this performance loss, sophisticated direct memory access controllers will include a facility to perform parameter reloads autonomously at the end of a block transfer. Thus, the central processing unit is only required to set up the channel parameters and reload parameters once during system initialization and is relieved of the direct memory access service activity during active operation. The interrupt from the direct memory access to the central processing unit at the end of a buffer transfer serves only for synchronization between the central processing unit and direct memory access unit 201, informing the central processing unit that new data is available. It is easy to extrapolate a similar buffering scheme for buffers of output data as well.
While effective in many situations, an auto-reload facility within a direct memory access unit can be limited. First, the direct memory access unit may only reload from generally one location and thus the sophistication of supported transfers is limited. Secondly, auto-reload facilities cannot be dynamically updated during active operation without central processing unit intervention which again degrades system performance.
A more generic solution that can be implemented is to allow the direct memory access unit itself memory-mapped access to its own channel parameters. By providing such access, a direct memory access channel can be initialized by itself or by another direct memory access channel. This facility provides greater flexibility than auto-reload facilities, because parameter reloads can occur from any location to which the direct memory access has access. Additionally, reloads can occur at any time, as opposed to the restriction of block boundaries to which auto-reloads are subject. An example of the memory-mapped solution will now be described.
Consider a multi-channel direct memory access. One of the channels is programmed to move real-time analog-to-digital data to memory as described above. The second channel is programmed to copy reload parameters from system memory to the first channels parameter storage elements. In this example, consider that the second channel is triggered by the end-of-block condition of the first channel. When the block is completed in the first channel, the second channel starts up and reloads the parameters for the first channel by reading them from system memory and writing them directly to the first channel parameter storage elements. These new parameters may point to a different buffer and thus the same function as the aforementioned double-buffering scheme can be replicated.
The advantage of this technique over the auto-reload technique is that the updated parameters are stored in system memory. Thus the central processing unit may access these parameters more quickly than it can access the direct memory access unit registers. Additionally, having the parameters updated from any memory allows much greater flexibility than limiting reload from a fixed location. For example, the second direct memory access channel may be able to walk through a set of reload parameters in memory as opposed to always copying from the same set. This allows the central processing unit the ability to set up a linked list of transfer parameters which the first channel will perform. This would not be possible with the simple auto-reload facility.
An example of this operation is illustrated in 300 of FIG. 3. Channel 0 having a data transfer count of zero is the condition activating a request event for channel N. Channel N responds by copying reload parameters from system memory to the address and data transfer count registers of channel 0. Many elaborate schemes are possible using this method, such as circular buffering, scatter-gather operations, data pooling, and self-modifying direct memory accesses.
It is clearly possible to provide the above advantages using only the central processing unit to perform the direct memory access channel parameter updates. However, this once again degrades system performance. By allowing the direct memory access unit access to its own registers, parameter updates can be performed autonomously. It is important to realize however either the central processing unit update method or the direct memory access updates method provides more flexibility than is possible with simple auto-reload from a fixed location.
The reload of parameters into a direct memory access unit has certain limitations. Since direct memory access is commonly used for servicing real-time events, care must be taken to ensure that parameter reloads occur during times when the direct memory access channel is idle. This reload must be guaranteed to complete before the channel begins active operation again. Failure to meet these requirements may result in lost or corrupted data streams which can cause the system to fail. Note this issue occurs because of the asynchronous operation of the central processing unit and the direct memory access unit. Because the central processing unit and the direct memory access channels operate in relative seclusion from one another, accesses to the channel parameters of a direct memory access unit must be carefully timed to occur during the aforementioned windows. This is often difficult to control, since the central processing unit or the reloading direct memory access channel may be busy performing other operations when a channel is ready to be reloaded. In the case of simple auto-reload, this is generally not an issue because the auto-loads is performed almost immediately.
FIG. 4 illustrates a classic timing window. Consider once again a direct memory access channel servicing a real-time data stream from an analog to digital converter. At the end of a complete buffer, the buffers must be ping-ponged and the central processing unit notified that new data is ready. Additionally, the direct memory access parameters must be reloaded to point to the other buffer. While the parameter updates are performed the analog to digital converter knows nothing of this and will continue to capture data and request service by the direct memory access unit. If a request is serviced by the direct memory access unit before the parameter updates have occurred, then data will be written to an invalid location potentially corrupting other system memory. Thus, the time between the last direct memory access transfer to one buffer and the first transfer to the next buffer is a critical timing window. The parameter updates must be guaranteed to occur during this timing window. At times t116 and t32 the channel 0 data transfer count 0 condition is active. The focus here is on the time instant t47447 at which critical timing window 450 begins. During this timing window 450, parameter updates must occur. Any updates occurring after the critical window 450 ends at time instant t48 will result in analog to digital converter data A2D being written to the wrong memory location.
Whether the direct memory access parameter updates occur via central processing unit access or using the memory-mapped direct memory access method, a reliable method of preventing the corruption of data streams or system memory must be provided. Traditionally, this has been achieved by the central processing unit disabling a direct memory access channel while it is reloaded, performing the parameter updates, and then re-enabling the direct memory access channel. This method can also be applied to the memory-mapped direct memory access unit access method. However, it costs more in terms of additional parameter storage required solely for the purposes of eliminating the timing window as compared to the storage costs of simply moving actual data in the system.
Because the direct memory access function of a digital signal processor is commonly used for servicing real-time events, care must be taken to ensure that any parameter reloads occur during times when the direct memory access channel is idle and must be guaranteed to complete before the channel begins active operation again. Failure to meet these requirements may result in lost or corrupted data streams, which can cause the system to fail. Accesses to the channel parameters of a direct memory access unit must be carefully timed to occur during well-defined timing windows or the timing window must be made non-critical or eliminated. Four direct memory access support features are described which allow for implementation of the solution of this invention. These are: request posting; parameter exhaustion; channel enable/disable; and parameter access.
To eliminate the timing window, it is necessary to disable the direct memory access channel whose parameters are to be updated during the update cycle. This ensures that no requests are processed until the new parameters have been written to the direct memory access unit channel parameters. The proposed method for timing window elimination in direct memory access units represents an efficient and elegant solution to this common direct memory access problem.